The design process for ASIC/FPGA's typically entails writing HDL code, creating a testbench of signal drivers and monitors and simulating the HDL code using the testbench. If design deficiencies are discovered during simulation, HDL code modifications are made and the design resimulated. Though this process is quite effective for developing the HDL code, it does present a few shortcomings.

First, when a simulation fails, the fault may lie in either the design or the testbench. The designer really ends up debugging two things simultaneously, rather than debugging just the design itself. This often results in longer initial debug times due to the need to wring out testbench problems.

Second, because of the effort involved in developing testbenches, a testbench for each piece of a design are rarely developed. Instead, several "mid-level" or "block" testbenches are created along with a top-level testbench. The idea of the block testbenches is to provide lower-level control and visibility into the inner parts of a design that cannot be easily accomplished with a top-level testbench. Typically, the block testbenches test a small hierarchical section of a design. The downside of this approach, besides the time and effort involved in developing the block testbenches, is that many pieces of the design must be developed before any testing can be performed. Additionally, the block testbenches can rarely fully test a block.

A more ideal process would allow the developer to perform design testing as the code is being written, preferably without the need to create a separate testbench.

The X-Amin tool provides a wealth of analysis and diagramming functions to aid the designer in identifying design flaws early in the design cycle - concurrent with the coding process. By adding X-Amin to the development process, designers will be able to more effectively develop bug-free code before beginning simulation.