Limitations

Although X-Amin supports parsing of the complete Verilog language, many language constructs are not supported for analysis. In general, X-Amin only supports synthesizable constructs for analysis purposes, but some of those constructs have additional limitations. Support for many of these will be added in the future. These limitations are detailed below.

 

Analysis limitations of Verilog constructs:

  • Tasks and functions
    • currently not supported
  • For-loops
    • currently not supported
  • Left-hand-side Concatentions
    • Bit-slices within the LHS concatenation are currently not supported.
  • Blocking assignments
    • Handled as non-blocking assignments