Change Log
Change Log
Version 3.2.23 Mar. 23, 2003
| VHDL Translator Changes/Fixes | |
| - Fixed handling of records yet again | |
Version 3.2.22 Feb. 20, 2003
| VHDL Translator Changes/Fixes | |
| - Fixed handling of records | |
Version 3.2.21 Jan. 04, 2003
| VHDL Translator Changes/Fixes | |
| - Corrected handling of nested subtypes | |
| - Corrected processing of bit references within arrays | |
| - Corrected parsing of attributes that looked like characters, i.e. Character'('a') | |
Version 3.2.20 Dec. 16, 2002
| General Changes/Fixes | |
| - Fixed bug which caused X-HDL to crash on a syntax error | |
| - Made X-HDL co-exist better with a previously installed perl | |
| VHDL Translator Changes/Fixes | |
| - Corrected erroneous inclusion of posedge/negedge on rising_edge/falling_edge function calls. | |
| - Changed processing of an integer subtype. If the range can be determined, it is converted to a reg/wire, otherwise, it is declared as an integer. | |
| - Improved record handling | |
| - Corrected sizing of integer subtypes | |
| - Corrected constant symbol lookup in evaluation subroutine | |
| - Fixed repetitious generation of array variable access/update | |
| - Added support for END RECORD <name>; | |
Version 3.2.18 June 22, 2002
| VHDL Translator Changes/Fixes | |
| - Added support for 'REVERSE_RANGE attribute | |
| - Corrected Constant->`define translation for non-integer constants | |
| - Corrected symbol-table lookups of sub-program calls where the sub-program is a Verilog reserved word | |
| - Corrected processing of falling_edge and rising_edge which occur within a WAIT statement | |
| - Corrected translation of REPORT. It was creating an extra trailing quote - seems to be a perl bug | |
Version 3.2.17 June 7, 2002
| General Changes/Fixes | |
| - Changed processing of X11 command-line arguments so that the GUI would not be started in command-line mode | |
| VHDL Translator Changes/Fixes | |
| - Corrected translation of `defines which are assignment targets. The `define was confusing the logic which handles signals that are assigned both sequentially and concurrently. | |
Version 3.2.16 June 4, 2002
| VHDL Translator Changes/Fixes | |
| - Changed parser so that is supports a conditional assign which does not contain a closing ELSE | |
Version 3.2.15 June 3, 2002
| General Changes/Fixes | |
| - Added option to remove X-HDL generated header comments - New command-line options: +no_header, -no_header | |
| - Added support for libraries named 'work'. If not defined, 'work' defaults to the destination directory. | |
| - Changed the database generation routines to be faster (Data::Dumper) | |
| VHDL Translator Changes/Fixes | |
| - Removed 'sigreg' option. This is now handled automatically and handling of split signals is improved | |
| - Added capability to inline packages rather than using `include. New command-line options: +pkg_inline, -pkg_inline | |
| - Added ability to translate constants to `defines. New command-line options: +defines, -defines | |
| - For packages with constants mapped to `defines, a separate file is generated which is `included prior to modules declarations for and module that uses the package. | |
| - Corrected handling of Generics containing and range specification | |
Version 3.2.14 May 27, 2002
| General Changes/Fixes | |
| - Corrected processing of user-specified libraries | |
| - Corrected configuration save/load operation | |
| - Corrected identification of demo mode | |
| - Added make_lib.pl to the distribution | |
| - Split XHDL packages into 'synthesizable' and 'non-synthesizable' | |
| - Changed line wrap so that wrap point is user-selectable.
Deleted +wrap command-line option and changed -wrap command-line option to -wrap <#> where # indicates the wrap point |
|
| - Changed line wrap algorithm to be a little more intelligent in picking the wrap point. | |
| VHDL Translator Changes/Fixes | |
| - Added support for a signal split between concurrent assignments and sequential assignments, new command-line option 'sigreg' | |
| - Changed conversion of a NULL statement from 'begin ; end' to 'begin end' | |
| - Corrected a misconversion of parenthesis-to-parenthesis when it should have been parenthesis-to-bracket | |
| - Added a user option to convert assignments in non-clocked
sequential blocks to blocking or non-blocking assignments for synthesizable code. Added new command-line options +blockseq and -blockseq |
|
Version 3.2.13 April 29, 2002
| General Changes/Fixes | |
| - Changed handling of pre- and post-processing functions under windows. Note: Windows-based perl pre- and post-processing scripts need to be run under Activestate Perl 5.6.1 build 631 or later. | |
Version 3.2.12 April 25, 2002
| VHDL Translator Changes/Fixes | |
| - Corrected processing of the range of a record element | |
| - Corrected conversion of aliases to `defines | |
Version 3.2.11 April 24, 2002
| VHDL Translator Changes/Fixes | |
| - Corrected generation of database information - sized constants were written incorrectly | |
| - Filtered out new namespace creation from a subprogram declaration in a package. | |
| Verilog Translator Changes/Fixes | |
| - Added an xhdl_timescale constant to the translated VHDL when `timescale is defined in the source | |
| - Corrected parameter override operation - it was being incorrectly identified as a delay value | |
Version 3.2.10 April 23, 2002
| VHDL Translator Changes/Fixes | |
| - Corrected base-type determination of constants | |
Version 3.2.9 March 23, 2002
| VHDL Translator Changes/Fixes | |
| - Corrected inappropriate changing of '<=' to '=' inflicted from 3.2.8 changes | |
| - Corrected internal flag control for sub-type declarations | |
| - Corrected processing of an enumerated type | |
Version 3.2.8 Feb. 27, 2002
| VHDL Translator Changes/Fixes | |
| - Corrected assignment to bits within an array | |
Version 3.2.7 Feb. 6, 2002
| VHDL Translator Changes/Fixes | |
| - Corrected generation of the symbol database. Symbol values containing a single-quote caused syntax errors in the database | |
Version 3.2.6 Feb. 2, 2002
| VHDL Translator Changes/Fixes | |
| - Corrected processing of a comment containing a single-quote | |
Version 3.2.5 Feb. 1, 2002
| VHDL Translator Changes/Fixes | |
| - Corrected a severe error with processing of a range constraint | |
Version 3.2.4 Jan. 28, 2002
| VHDL Translator Changes/Fixes | |
| - Corrected processing of 1'b0 in a not-equal (/=) expression | |
| - Fixed xhdl_function pragma | |
Version 3.2.3 Jan. 21, 2002
| VHDL Translator Changes/Fixes | |
| - Corrected type processing for a type defined within a named block | |
| - Corrected processing of a concatenation when it occurs within a filtered function call | |
Version 3.2.2 Jan. 12, 2002
| General Changes/Fixes | |
| - Corrected decimal-to-binary conversion of 0 (zero) | |
| VHDL Translator Changes/Fixes | |
| - Corrected clock-edge detection logic for 'wait until' statements | |
| - Corrected translation of array ranges | |
| Verilog Translator Changes/Fixes | |
| - Corrected sizing of operands to a conditional assign | |
Version 3.2.1 Dec. 4, 2001
| General Changes/Fixes | |
| - Corrected invocation of the Help Browser on the Windows platform | |
| VHDL Translator Changes/Fixes | |
| - Corrected handling of uninitialized generics | |
| - Corrected internal setting of namespace which affected evaluation of generate expressions | |
Version 3.2.0 Nov. 18, 2001
| - Initial Release |