FAQ
FAQ
What are the restrictions of Demo Mode?
X-HDL contains a demonstration mode that allows you to run the
tool, with some restrictions, when either you are trying out the
tool to see how well it will meet your needs, or when a product
license is not currently available. In demo mode, the translator
is fully functional except that the file size is restricted in GUI mode and the
tool will not run in batch mode. VHDL
files smaller than 300 tokens and Verilog files smaller than 200 tokens can be processed in GUI mode
normally. Larger files can be processed but the output is restricted to
window viewing only. A token is defined as a language keyword, an
identifier, operator, or punctuation character. Comments do not
count as tokens.
What information from my computer do I need to obtain an
evaluation/permanent license?
To generate a license for your copy of X-HDL, X-Tek needs to know the
host ID of your computer, or the C: drive volume serial number if the platform
is a PC running Windows. The easiest way to find the host ID of your machine is
to run the lm_hostid program included with X-HDL. This method works for PCs as
well as Unix machines. To find the C: drive volume serial number on a PC, open a
DOS window and do a "dir" command. The volume serial number will be printed at
the top of the directory listing.
We are currently using X-HDL version ***. Is a more recent version is
available?
The most recent version of X-HDL is always available on the X-Tek
web-site at:
www.x-tekcorp.com
Do you have a list of supported and non-supported constructs for
translation?
Although this is an often requested item, X-Tek has resisted creating
such a document because regardless how the information is presented it tends to
be misleading. X-HDL performs "intelligent" translation rather than simple
syntax conversion. Because of this, the translation process can be sensitive to
coding style as well as the way constructs are used.
In general, any synthesizable code should be 100% translatable by X-HDL.
Why X-HDL is inserting strange functions into my resultant VHDL code?
When X-HDL translates Verilog to VHDL, it often needs to convert one
type to another. To do so, it uses X-Tek created functions. These functions can
be found in the packages located in the $XTEK_HOME/lib/xtek
directory.
Why don't the source VHDL package functions appear in the resultant
Verilog?
VHDL package information is included in the resultant code using the
`include compiler directive. If your translated code does not contain a `include
for the desired package check the following:
1) Make sure the package has been translated
2) Make sure you have specified a
library mapping for the package
Why doesn't the source Verilog `include file code appear in the resultant
VHDL?
This usually means that X-HDL could not locate the file specified in
the `include compiler directive.
My translated Verilog code doesn't contain the necessary Library or Use
clauses. Why not?
X-HDL does not assume any special libraries are needed. All necessary
libraries need to be specified by the user since often times the desired
libraries vary from user-to-user and system-to-system. Note that the
libraries/packages need only be entered once. They can then be saved with the
other translation options using the Setup->Save pull-down menu.
Why are my Verilog parameters being translated into VHDL generics?
Any parameters defined immediately after the port-list of a module
definition are subject to being overridden by the parent module in Verilog using
the #(..) syntax. To retain this capability in the resultant VHDL code, those
parameters are translated to VHDL generics. To prevent a parameter from being
translated as a generic make sure at least one input/output/inout declaration
preceeds it in the code.
Why don't my Verilog `define directives get translated to VHDL constants?
Verilog `define directives are actually text replacement macros, not
constant definitions. Therefore, during the translation process X-HDL replaces
the defines with the specified text.