VHDL Packages

In nearly all VHDL designs, packages need to be included in the design. These packages usually contain type definitions and conversion functions. The translated VHDL code is no different - it too must have package definitions. However, many VHDL systems are different and require different packages to be included. Therefore, X-HDL does not automatically include the necessary package information to the translated code. Rather, the user can specify the packages to be included and X-HDL will add those to the code. In GUI mode, the packages are added with the 'Add Package' menu in the Verilog translation perferences menu. In batch mode, the packages are defined using one or more +/-pkg command line options.

In both the GUI and batch mode cases, the package definition is the same - a fully qualified package name such as: IEEE.std_logic_1164.all

X-HDL will automatically separate out the library name (IEEE, in this case) and add a library clause to the code. If more than one package is used from any library, the library clause is only generated once.

During Verilog to VHDL translation, some conversion functions may need to be added to the code to account for Verilog's inherent type-casting abilities. X-HDL includes several packages of conversion functions separated by VHDL type. These packages are:

• XHDL_bit.vhdl
• XHDL_std_logic.vhdl
• XHDL_std_ulogic.vhdl

X-HDL also contains a package of conversion functions for reals, integers and such. This package is named:

• XHDL_misc.vhdl

The X-HDL packages can be found in the $XTEK_HOME/lib/xtek directory. If you want any of these package definitions included in your source code, you must specify it just like any other package.