X-HDL screenshots:

• Verilog-to-VHDL main window
• VHDL-to-Verilog main window

X-HDL Features

X-HDL VHDL Support

X-HDL User's Manual (pdf)

X-HDL 4 Change Log

Download X-HDL

X-HDL Project Tracking

Purchase X-HDL

Verilog Language Support

X-HDL provides push-button translation of RTL and gate-level Verilog code to VHDL. Except for user-defined primitives, the entire language is parsed by X-HDL, but not all constructs can be translated to VHDL. The following table provides an overview of the supported constructs. Note that some constructs may be more or less translatable depending on their context and use within the source code.

Component Instantiations
Gate Primitives
Wires/Regs/Arrays
Parameters
Always Blocks
Initial Blocks
If/Case Statements
Looping Statements
Continuous Assignments
Blocking/non-blocking Assignments
Compiler Directives
Tasks/Functions
System Tasks/Functions
LHS Concatenation
Delays
System Timing Checks
Verilog-2001	Most constructs supported
Fork/Join Blocks
Force/Disable/Release
Hierarchical Identifiers
UDP's

 

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