X-HDL screenshots:

• Verilog-to-VHDL main window
• VHDL-to-Verilog main window

X-HDL Features

X-HDL Verilog Support

X-HDL User's Manual (pdf)

X-HDL 4 Change Log

Download X-HDL

X-HDL Project Tracking

Purchase X-HDL

VHDL Language Support

X-HDL provides push-button translation of RTL and gate-level VHDL code to Verilog. Although the entire language is parsed by X-HDL, not all constructs can be translated to Verilog. The following table provides an overview of the supported constructs. Note that some constructs may be more or less translatable depending on their context and use within the source code.

Component Instantiations
Gate Primitives
Signals/Variables/Constants
Multi-dimensional Arrays
Generics
Processes
If/Case Statements
Looping Statements
Continuous Assignments
Generates
Report
Procedures/Functions
Overloaded Functions
Types/subtypes
Records
Delays
Packages
VHDL'87 & VHDL'93
Physical Types
File I/O
Allocators
Array Ports