X-HDL Language Support

X-HDL provides push-button translation of RTL and gate-level Verilog and VHDL code to VHDL and Verilog, respectively.

Except for Verilog user-defined primitives, the entire source language is parsed by X-HDL, but not all constructs can be translated to the target language. The following tables provide an overview of the supported constructs. Note that some constructs may be more or less translatable depending on their context and use within the source code.

Verilog Language Support

VHDL Language Support

Component Instantiations Gate Primitives Wires/Regs/Arrays Parameters Always Blocks Initial Blocks If/Case Statements Looping Statements Continuous Assignments Blocking/non-blocking Assignments Compiler Directives Tasks/Functions System Tasks/Functions LHS Concatenation Delays System Timing Checks Verilog-2001 Most constructs supported Fork/Join Blocks Force/Disable/Release Hierarchical Identifiers UDP's

Component Instantiations Gate Primitives Signals/Variables/Constants Multi-dimensional Arrays Generics Processes If/Case Statements Looping Statements Continuous Assignments Generates Report Procedures/Functions Overloaded Functions Types/subtypes Records Delays Packages VHDL'87 & VHDL'93 Physical Types File I/O Allocators Array Ports